1. Field of the Invention
The present invention relates to digital processing systems and, more specifically, to a system for configuring ports in a digital processing system.
2. Description of the Prior Art
Frequently, integrated circuits will employ several copies of the same logic that are physically separated by relatively large distances. For example, different partitions of an input/output module can be on opposite sides of an integrated circuit chip. Often, all of the partitions must initially be configured with a common set of data. Configuring such partitions can introduce complexity to the chip.
Several different approaches are used to configure different partitions on a chip with common initial data. One approach is to use a single set of registers and distribute the data from the set of registers to each partition. This approach has the disadvantage of requiring repowering of each data line and an increased wiring complexity in the chip. Another approach requires creating a plurality of copies of the registers and hard wiring each copy to a common set of data inputs. This approach is inflexible, in that the registers cannot receive data independently, and it results in increased wiring complexity. Yet another approach is to place all of the registers on a common data bus and assign common addresses to groupings of registers. This approach, while reducing the wiring problem, is also inflexible. With these solutions, the effect of the initial program load time can be compounded if the registers being targeted on one interface are used as interface registers to perform reads and writes to multiple other chips.
Therefore, there is a need for a system for writing common data units to a plurality of different registers without increasing on-chip wiring and while maintaining flexibility regarding use of the registers.